Controlling impurities in a wafer for an electronic circuit

ABSTRACT

Methods of processing a silicon wafer for an electronic circuit, substrates for an electronic circuit, and device manufacturing methods are disclosed. According to an embodiment the method of processing a silicon wafer comprises impregnating the silicon wafer with impurities that form one or more deep energy levels within the band gap of silicon, wherein at least one of said deep energy levels is positioned at least 0.3 eV away from the conduction band if the level is a donor level or at least 0.3 eV away from the valence band if the level is an acceptor level, wherein: said impregnating step is performed in such a way that the ratio between the maximum concentration of said impurities in said silicon wafer and the average concentration of said impurities in said silicon wafer is less than 7:1.

The present invention relates to a silicon wafer for use in the fabrication of electronic devices, for example semiconductor devices, particularly high frequency and/or high power electronic devices, and processing methods for improving the properties of the wafer by controlling the distribution of impurities therein.

Single crystal silicon grown by the Czochralski (Cz) technique is currently the most widely used semiconductor material for integrated circuits (ICs) in most applications. However, for higher frequency technologies, group III-V materials are generally preferred. This has meant that products such as mobile phones, which require both high and low frequency circuitry, are often constrained to using a hybrid arrangement, with group III-V semiconductors for the high frequency processes (e.g. front end signal processing in mobile phones) and silicon for the rest of the functionality of the device. Hybrid circuitry using group III-V semiconductors is complex and relatively expensive compared with solutions based on silicon wafers only. Group III-V materials also generally offer inferior thermal conductivity properties compared with silicon.

Recent improvements in silicon processing have led to an increase in the speed at which individual silicon devices can operate efficiently and the point has now been reached where individual Si-based devices are capable of operating at speeds approaching those of their III-V counterparts. However, using conventional production techniques, it is difficult to avoid the presence of background carriers in the silicon wafers. However high resistivity substrates are required for reducing transmission line losses, making high-Q inductors and minimising substrate crosstalk in high frequency applications and monolithic circuits. This degradation in the characteristics effectively prevents the use of silicon wafers for many high frequency devices.

To tackle these problems, several special processes have been described in the prior art for producing high resistivity substrates. These include the so-called float-zone (FZ) method for producing very high purity silicon and the “silicon-on-anything” (SOA) constructions in which a material other than a silicon wafer is used for the “handle” or base layer of the substrate (which is where most of the microwave power is absorbed).

Silicon wafers produced using the float-zone method can have resistivities of the order of 10 kΩcm or more, but their maximum diameter is typically limited to about 150 mm. This is unsuitable for modern VLSI technology where the standard wafer diameter is 300 mm. The other major problem of float zone wafers is the absence of oxygen, which internally getters metallic impurities in the substrate during device processing and improves reliability. Thus, float-zone substrates tend to have less reliable properties. There are also attempts to make high resistivity Cz silicon but these are presently limited to around 1 kΩcm and are more expensive than conventional Cz silicon wafers.

The use of thin films of GaN on silicon handle wafers is known for high power, high frequency architectures, but such approaches use relatively expensive float zone silicon.

The SOA technology uses an insulating material like quartz or glass for the handle layer instead of a silicon wafer, which has very different physical and thermal properties than silicon. This means processing apparatus and methods need to be adapted to the particular characteristics of the SOA devices. A further problem is the relatively high thermal resistances these devices present, which can be of the order of 15000 K/W rather than the usual 100 K/W. This can lead to substantial self-heating effects during operation and thermal runaway of devices even at low power levels.

Semicond. Sci. Technol. 18 (2003) 517-524 describes the use of deep level impurities to obtain “semi-insulating” (high resistivity) Czochralski (Cz) silicon. This academic study investigates values of deep impurity levels and their concentrations that are suitable for raising the resistivity of the silicon to near intrinsic levels. No details regarding commercial application of the technology are disclosed. Furthermore, the skilled person would be strongly disinclined to use the kind of impurities that act to increase the resistivity of silicon anywhere in a semiconductor manufacturing facility because of the risk of contamination of silicon device layers, which is known to seriously damage or destroy their performance.

WO 2009/034362 discloses the use of deep level impurities to increase the resistivity of a substrate for high frequency circuits, but requires full encapsulation of the substrate, and/or of a device layer mounted on the substrate, by a diffusion barrier layer. Furthermore, substrates manufactured according to the teaching of WO 2009/034362 can be sensitive to certain heat treatments that may be applied after the deep level impurities have been introduced into the substrate, for example to manufacture other elements of the electronic device of which the substrate is to be a part, or during operation of the electronic device. The subsequent heat treatments may cause the resistivity of the substrate to fall, in many cases to an unpredictable extent, which may reduce performance and/or affect reliability. It has also been found that a given process for impregnating a substrate with deep level impurities can result in a range of different resistivities, which hampers reliability and manufacturing efficiency (yield).

In the description which follows, reference to “silicon wafer” is understood to encompass both a whole (undiced) silicon wafer and a portion of a whole silicon wafer (for example a diced portion of a whole silicon wafer).

It is an object of the present invention to address at least some of the problems discussed above in relation to the prior art.

According to an aspect of the invention, there is provided a method of processing a silicon wafer for use in a substrate for an electronic circuit, comprising: impregnating the silicon wafer with impurities that form one or more deep energy levels within the band gap of silicon, wherein at least one of said deep energy levels is positioned at least 0.3 eV away from the conduction band if the level is a donor level or at least 0.3 eV away from the valence band if the level is an acceptor level, wherein: said impregnating step is performed in such a way that the ratio between the maximum concentration of said impurities in said silicon wafer and the average concentration of said impurities in said silicon wafer is less than 7:1.

The inclusion of impurities that form deep energy levels (“deep level impurities”) raises the resistivity of the silicon wafer layer and reduce the absorption of microwave power in high frequency applications by reducing the concentration of free carriers present in the material. High frequency circuits manufactured using such silicon wafers do not therefore suffer the same reduction in performance that is known in single crystal silicon wafers that do not contain such impurities. Thus, devices comprising high and low frequency parts can be made entirely using silicon-based substrates, thus obviating the need for hybrid circuitry and thereby achieving greater simplicity and reduced cost of manufacture.

Embodiments of the present invention provide an improvement over arrangements which rely on very low doped (and thus high resistivity) float zone silicon for the substrate. In such systems, free charges can be induced by the presence of electric fields produced by operation of the electronic circuit. These fields tend to move the band edge in the silicon wafer closer to the Fermi level and so induce free carriers, which in turn lower the resistivity of the material. The substrates according to embodiments of the present invention may be resistant to the formation of such carriers because the deep level impurities act to “pin” the Fermi level close to the centre of the gap.

Controlling the impregnation step so that the ratio of the maximum impurity concentration to the average impurity concentration is less than 7:1 improves performance, reliability and/or flexibility. In essence this step increases the uniformity of the spatial concentration distribution of the deep level impurities within the silicon wafer, which reduces the possibility of, and/or the extent to which, regions in the silicon wafer that are at the tail ends of the concentration distribution (i.e. the regions having the lowest and highest concentrations) might behave differently and/or unpredictably in comparison to the rest of the silicon wafer. In particular, where the concentration is too low, compensation of carriers may not be sufficient, leading to reduced resistivity. By contrast, concentrations that are too high may trigger clustering of the impurities, depending on the nature (e.g. temperature profile) of any processing steps that are performed after the impregnation. Clustering can interfere with the mechanism by which the deep level impurities increase the resistivity of the silicon wafer, leading to reduced resistivity. Increasing the uniformity of the deep level impurity distribution helps to avoid these upper and lower limits, which improves reliability.

In the absence of the controlled impregnation step (to increase uniformity), the distribution of impurities will often take a U-shaped profile (particularly for impurities that diffuse by the kick-out or Frank-Turnbull mechanisms) having increased concentrations near the surfaces of the silicon wafer. The relatively large variation in concentration associated with the U-shaped profile makes it difficult to avoid the above-mentioned upper and lower limits. If the overall amount of impurities is too low, the concentration in the bulk of the silicon wafer will tend to be too low to compensate free carriers properly and the resistivity will be too low. In contrast, if the overall amount of impurities is too high, the concentration near the surfaces will tend to cause clustering during later processing or use of the device. The clustering will tend to occur near to the device layer (because this will be near to a surface of the silicon wafer) where loss of resistivity is likely to be particularly damaging to the device performance.

Optionally, the wafer is formed from silicon grown using the magnetic Czochralski method. Such wafers have lower levels of oxygen and are particularly advantageous where Au is used as the deep-level impurity because the rate of injection of self interstitials, which tend to displace Au atoms from substitutional sites, is reduced.

According to an alternative aspect of the invention, there is provided a substrate for an electronic circuit, comprising: a silicon wafer impregnated with impurities that form one or more deep energy levels within the band gap of silicon, wherein at least one of said deep energy levels is positioned at least 0.3 eV away from the conduction band if the level is a donor level or at least 0.3 eV away from the valence band if the level is an acceptor level, wherein: the ratio between the maximum concentration of said impurities in said silicon wafer and the average concentration of said impurities in said silicon wafer is less than 7:1.

According to an alternative aspect of the invention, there is provided a device manufacturing method, comprising the following steps: impregnating a silicon wafer with impurities that form one or more deep energy levels within the band gap of silicon, wherein at least one of said deep energy levels is positioned at least 0.3 eV away from the conduction band if the level is a donor level or at least 0.3 eV away from the valence band if the level is an acceptor level; and forming a device layer comprising electronically functional components, wherein: said impregnating step is performed in such a way that the ratio between the maximum concentration of said impurities in said silicon wafer and the average concentration of said impurities in said silicon wafer is less than 7:1.

According to an alternative aspect of the invention, there is provided a method of processing a silicon wafer for use in a substrate for an electronic circuit, comprising: impregnating the silicon wafer with impurities that form one or more deep energy levels within the band gap of silicon, wherein at least one of said deep energy levels is positioned at least 0.3 eV away from the conduction band if the level is a donor level or at least 0.3 eV away from the valence band if the level is an acceptor level; and after the impregnating step: removing a layer at the surface of the silicon wafer by etching; or performing an anneal to redistribute said impurities away from a surface layer.

The surface layer removed by etching may consist of the deep-level impurities only or may comprise a mixture of the deep-level impurities and silicon, for example.

The inventors have recognized that processing at elevated temperatures (such as the temperatures that would be used in typical device manufacturing steps) of silicon doped with deep level impurities, for example Au, can cause a thin deep-level impurity rich layer to be produced at the surface of the material. The etching and/or anneal reduces the concentration of deep-level impurities at or near the surface and reduces any deleterious effect on performance. Optionally, the anneal for redistributing impurities away from a surface layer is carried out at about 1150 degrees C. for a short period, for example about two to five minutes, followed by rapid cooling, for example at about 40 degrees C. per minute or more for at least a proportion of the cooling, for example down to about 650 degrees C.

According to an alternative aspect of the invention, there is provided a device manufacturing method, comprising the following steps: impregnating a silicon wafer with impurities that form one or more deep energy levels within the band gap of silicon, wherein at least one of said deep energy levels is positioned at least 0.3 eV away from the conduction band if the level is a donor level or at least 0.3 eV away from the valence band if the level is an acceptor level; forming a device layer comprising electronically functional components; and after the impregnating step: removing a layer at the surface of the silicon wafer by etching; or performing an anneal to redistribute said impurities away from a surface layer.

Embodiments of the invention will now be described, by way of example only, with reference to the accompanying schematic drawings in which corresponding reference symbols indicate corresponding parts, and in which:

FIG. 1 is a schematic illustration of a substrate incorporating a silicon wafer processed according to an embodiment of the invention;

FIG. 2 is a schematic illustration of how the distribution of deep level impurities in a silicon wafer can be described in terms of maximum and minimum concentrations and by reference to geometrical parameters for the silicon wafer;

FIG. 3 illustrates a method for introducing deep level impurities that avoids or attenuates a U-shaped concentration profile;

FIG. 4 illustrates an alternative method for introducing deep level impurities that avoids or attenuates a U-shaped concentration profile;

FIG. 5 illustrates an alternative method for introducing deep level impurities that avoids or attenuates a U-shaped concentration profile;

FIG. 6 is a schematic illustration of a silicon wafer with a source layer of impurity and a diffusion-inhibiting layer in between the source layer and the silicon wafer; and

FIG. 7 is a graph to compare resistivity versus gold dopant concentration for a nominally n-type silicon wafer and a nominally p-type silicon wafer.

As has been discussed above, at high frequencies silicon wafers become problematic because of high absorption of microwave power by background free carriers of the material, causing a reduction in the performance of the complete circuit.

Silicon has a relatively low band gap of 1.12 eV at room temperature, which sets its intrinsic (100% pure material) free carrier concentration at 10¹⁰ cm⁻³ and hence its nominal resistivity at 300 kΩcm or greater. However, it is extremely difficult to avoid background impurities being incorporated into the silicon during single crystal growth (particularly with the otherwise highly favourable Czochralski (Cz) growth method), and in practice it is very challenging to reduce the free carrier concentration much below 10¹³ cm⁻³.

For radio frequency CMOS devices operating up to around 2 GHz, special high resistivity silicon tends to be used, which has a resistivity of around 1 kΩcm. However, it has been shown that a silicon wafer resistivity of at least 1 kΩcm is required for satisfactorily low absorption loss and operation comparable with GaAs (a group III-V material) substrates, for example, operating at frequencies of more than a few MHz.

Embodiments disclosed herein may optionally include substrates of the “silicon-on-insulator” (SOI) type. These substrates comprise a silicon wafer layer, also known as a handle wafer, and an insulating layer on top of the silicon wafer and presenting an outer surface for a device layer, within which electronically functional elements of the device are to be formed. Where a high frequency device is to be formed in the device layer, it is the resistivity of the silicon wafer layer that is the determining factor in the absorption loss of the SOI circuit. The presence of the insulating layer, which separates the device layer from the silicon wafer layer may also be chosen to have diffusion barrier properties, which allows greater flexibility in modifying the properties of the silicon wafer layer without affecting or contaminating the devices made in the device layer.

An advantage of adapting SOI substrates to high frequency technology is that this field of technology is reaching maturity, and the use of SOI substrates is already routine and looks likely to become the industry standard for many future applications. In addition, unlike SOA substrates, SOI substrates are largely compatible with existing silicon processing tools (due to the much greater similarity of SOI substrates with standard silicon wafers (including their thermal properties for example).

The present invention is based on introducing deep level impurities into the wafer layers (e.g. the Cz silicon layers) of substrates (e.g. SOI substrates) in order to compensate the free carriers remaining after the single crystal growth process of the silicon wafers. In this way, it is possible efficiently to produce silicon wafers of extremely high resistivity (thus reducing absorption losses) and of dimensions and physical properties suitable for conventional semi-conducting processing systems.

FIG. 1 is a schematic illustration showing the structure of a substrate 2 for an electronic circuit, comprising a silicon wafer layer 4 and an electrically insulating layer 6, formed on a surface of the silicon wafer layer 4. The insulating layer 6 provides a surface on which a device layer 8 may be formed (comprising device structures formed in a layer of high purity silicon, for example). In addition to being electrically insulating, the insulating layer 6 may have the property of inhibiting or preventing diffusion of impurities from one side of the layer to the other (i.e. rendering the rate of diffusion of the relevant impurities so slow that little or no impurity reaches the device layer 8, such that the device layer 8 is not significantly affected by contamination), in which case the insulating layer 6 may also be referred to as a “diffusion barrier layer”. The combination of silicon wafer layer 4, insulating layer 6, and device layer 8 may together form an SOI type device, for example. The insulating layer 6 may be formed of an oxide of the wafer material, for example silicon oxide (which may be obtained simply by exposing the wafer layer 4 to air at elevated temperatures, for example). Silicon nitride and/or silicon oxynitride may also be used for the insulating layer 6 (diffusion barrier layer). Other materials that are insulating and which inhibit the diffusion of the impurities from the silicon wafer layer 4 to the device layer 8 may also be used.

The silicon wafer layer 4 is impregnated with impurities that produce deep energy levels, thereby increasing the resistivity of the silicon wafer layer 4.

The concentration of deep level impurities may be chosen to be in the range of 10¹³ to 10¹⁸ cm⁻³. Preferably, the concentration is in the range of 10¹⁴ to 10¹⁷ cm⁻³. More preferably, the concentration is in the range of 10¹⁴ to 10¹⁶ cm⁻³. The impurities may preferably increase the resistivity to at least 1 kΩcm, more preferably to at least 2 kΩcm, more preferably to at least 4 kΩcm, more preferably to at least 10 kΩcm, at the operating temperature of the high frequency device, for example at about 293 K, 323 K or 353 K. Preferably, the impurities may increase the resistivity to at least 100 kΩcm at room temperature. Any combination of the above concentrations, resistivities and temperatures may be used.

The impurities are effective to increase the resistivity because they act to compensate for shallow donor and acceptor levels that arise in the band gap of the material (e.g. silicon) of the substrate layer 4 due to background impurities (also referred to as “shallow level dopants”) introduced during the manufacturing process of the silicon wafer layer 4. For example, where the Cz technique is used to fabricate the silicon wafer layer 4, shallow level dopants such as phosphorous and boron are common. It is extremely difficult to eliminate such background impurities from the manufacturing process. Other shallow levels may also be introduced during the manufacturing process. For example, thermal donors may be formed during the processing of Cz silicon and these will also be compensated by the intentionally introduced deep level impurities.

In general, the effect on the resistivity of the impurities which are deliberately added to increase the resistivity will depend on the type of impurity and on the concentration of the impurity. The type of impurity determines the nature of the energy levels that the impurity introduces into the band structure of the material forming the silicon wafer 4. Broadly speaking, where an energy level is formed which is relatively close to either the valence or conduction band, the effect of the impurity on the resistivity tends to vary significantly as a function of the concentration of the added impurity. On the other hand, where impurities are chosen which introduce energy levels deep within the band gap, a rise in resistivity is achieved over a broader range of concentrations of the added impurity. Impurities which introduce one or more energy levels deep within the band gap are referred to as deep level impurities and are in general preferred over shallower level impurities (which are nevertheless deep enough to provide some increase in resistivity) because the increased resistivity occurs over a broader range of concentrations and is also less sensitive to the concentration of the shallow level dopants that are being compensated.

Further details about the expected effect of different deep level impurities on the resistivity of Czochralski silicon can be found in the research paper Semicond. Sci. Technol. 18 (2003) 517-524, herein incorporated in its entirety by reference, the teaching of which can be applied to the impurities used in the present invention.

A number of potentially suitable deep level impurities exist. These include gold, silver, chromium, cobalt, palladium, platinum, vanadium and manganese. The effect on the resistivity of silicon of such materials has meant that they have traditionally been excluded from semiconductor manufacturing facilities because of the risk of contamination of silicon device layers. This is particularly true for gold and silver which have very high diffusivities, which increases the risk that they will find their way into the device layers. A possible exception is the fast switching diode, for which Au is deliberately introduced as a “lifetime killer” (to reduce minority carrier lifetime). However, this is unusual. In general, the presence of a lifetime killer is considered highly undesirable and great care is taken to avoid them. Embodiments of the present invention have been developed despite this commonly held fear in the field, based on recognition that a broad class of devices are insensitive to the deep level impurities (e.g. passives) and that, for devices which are sensitive, careful positioning of the devices relative to impregnated wafers, careful design of substrates (e.g. to include diffusion barrier shields) and/or careful choice of manufacturing sequences can sufficiently reduce the risk of performance disruption due to contamination of device layers by the deep level impurities.

The deep-level impurities may be chosen so that the impurity energy levels pin the Fermi level near the middle of the band gap. The pinning of the Fermi level in this way may prevent the production of an inversion layer that is sometimes produced in SOI wafers adjacent to the dielectric layer. This is a significant problem as the inversion layer may otherwise reduce the effective substrate resistance in high resistivity silicon substrates with low background doping and can be a particular problem when float-zone material is used in this role.

Whether or not the energy level introduced by a given impurity is deep enough to increase the resistivity of the silicon wafer layer will depend on the nature of the silicon wafer layer 4 and how it was manufactured (i.e. on which shallow level dopants are intrinsically present and in which concentrations—both the energy level of the impurity and its concentration are relevant factors). However, it is typically expected that impurities having energy levels which are more than 0.3 eV deep in the band gap (the relevant depth being the energy difference between the deep level and the conduction band for donor states and between the energy level and the valence band for acceptor states) would be suitable. Larger separations (i.e. deeper energy levels) generally produce higher resistivity material over a larger range of concentrations. As an example of a suitable concentration for a particular application, theory suggests that a concentration of 5×10¹³ cm⁻³ of boron would require about 10¹⁵ cm⁻³ of gold to produce satisfactory compensation. However, a higher concentration of Au would result in an even higher resistivity. The inventors have found that compensation works better for n-type rather than p-type material. Therefore, it may be desirable to start with an n-type material (e.g. phosphorous doped) of about 1×10¹⁴ cm⁻³. This approach can result in resistivities greater than 100 kOhmcm at room temperature.

Deep level impurity dopants are found to fall into two broad categories according to the nature of compensation produced. For the addition of Au or Ag to p-type substrates, the resistivity saturates with increasing concentrations of the deep dopant, whereas for Mn and V the resistivity peaks and then tails off quickly with increasing deep dopant concentration. The different behaviour is due to the presence of both acceptor and donor states very near mid-gap for the first category of impurities, whilst the second type only have a single type of level very near mid-gap. The first category of impurities can trap both electrons and holes and are thus able to compensate, for example, for the presence of residual boron atoms in Cz-Si and also any thermal donors which might be formed during processing. The second category can only compensate for a single carrier type. From this picture, using the first category of dopants, for which resistivity saturates at high impurity concentrations, it can be easier to achieve uniformly high resistivity in the substrate without requiring precise control over the spatial distribution of the compensating deep impurity concentration.

The properties of Au make it a particularly promising candidate for the deep level impurity. Assuming that a minimum guaranteed concentration of residual B that can be achieved in Cz-Si, at reasonable economic cost, is 5×10¹³ cm⁻³, it is expected that introduction of about 10¹⁶ cm⁻³ Au atoms into the silicon wafer will achieve a resistivity greater than about 3 kΩcm at room temperature.

From the solubility of Au in Si, calculated using thermodynamic data and an experimentally derived phase diagram, it is expected that temperatures of around 1000° C. would be required to introduce gold concentrations up to 10¹⁶ cm⁻³, whilst at 1200° C. the solubility is around 10¹⁷ cm⁻³, much more than sufficient to compensate low B doped Cz-Si, although the effects of clustering may become relevant at these higher concentrations (see below).

Diffusion of Au in bulk Si occurs by either the dissociative Frank-Turnbull mechanism or by the kick-out mechanism. At temperatures above around 800° C., the kick-out mechanism dominates. Au diffuses very quickly as an interstitial but its interstitial solubility is very low whereas substitutional Au is a slow diffuser, but has a much higher solubility. Thus the transport of Au involves three stages: i) rapid interstitial diffusion, ii) the interchange between interstitial and substitutional states by the kick-out mechanism, which creates a super saturation of self-interstitials and finally, iii) the out-diffusion of these self-interstitials to the Si surface, which is normally assumed to act as an infinite sink. This last step is usually rate limiting and results in a “U-shaped” concentration profile (i.e. with higher concentrations near the surfaces of the Si and a lower concentration trough towards the centre of the Si away from the surfaces), typical of Au diffusion in Si. More generally, the U-shaped concentration profile will arise for Au, Pt, Zn, for example, which diffuse by the kick-out mechanism, and Ni, for example, which diffuses via the Frank Turnbull mechanism.

The effective diffusivity of Au does not depend on the diffusivity of any Au species, but only on the diffusivity of Si self-interstitials and the equilibrium concentrations of Si self-interstitials and substitutional Au. Transport of Au to both surfaces of silicon wafers, from a single surface, is rapid but it takes longer for the Au concentration in the centre of the silicon wafer to reach its solid solubility value.

The resistivity of Si can be calculated for different concentrations of Au according to the compensation mechanism detailed in K. Mallik, R. J. Falster, and P. R. Wilshaw, Semiconductor Science Technology, 2003. 18: p. 517. When this analysis is combined with expressions for Au concentration obtained after diffusion, the resistivity at any depth in a silicon wafer can be calculated. For example, assuming a silicon wafer with a background B concentration of 5×10¹³ cm⁻³, and using values for the Au donor and acceptor energy levels of E_(v)+0.35 and E_(c)−0.55 eV, resistivity in excess of 3 kΩcm should be possible throughout the silicon wafer, after an anneal of 40 minutes at 1050° C.

A number of standard approaches are available for incorporating the deep level impurity atoms. For example, the impurities may be deposited on the surface of a raw wafer (e.g. a Cz-produced single crystal silicon wafer) in a concentrated form and left to diffuse into the bulk at elevated temperatures. The speed of this process could be increased by increasing the temperature, for example. Alternatively, ion implantation may be used to introduce impurities into the silicon wafer followed by anneal to in-diffuse the impurities.

The device layer 8 may be formed using an additional silicon wafer. In a first step, the silicon wafer 4 and the additional silicon wafer are oxidised so as each to be covered by an oxide layer (layer 6 on the wafer 4). The oxidised wafers are then brought into contact with each other and heated so that a glass is formed from the oxide in the region between the wafers. The glass acts to bond the wafers together and also constitutes a diffusion-barrier-insulating layer. The upper surface may then be cut to expose a clean layer of silicon within which electronically functional device structures may be formed to create the device layer 8. In the example described, both wafers are oxidized before they are bonded together. However, according to a variation, only one of the two wafers may be oxidized prior to bonding.

The diffusion barriers must prevent the transport of deep level impurities (e.g. Au) through the layers for the thermal budget which is necessary for device processing after the deep level impurities have been introduced. This will vary according to the stage of the processing at which the deep level impurities are introduced and the nature of the devices to be fabricated.

It is expected that a 147 nm thick thermal silicon oxide layer could work as an effective diffusion barrier for Au for 1 hour at 1000° C., but would fail at 1050° C.

Alternatively or additionally, the device layer 8 may comprise passive electronic components (such as resistors, capacitors or inductors) that are not affected by the deep level impurities. Such passive electronic components may be formed directly on the silicon wafer 4 or on a dielectric layer deposited on the surface of the silicon wafer 4.

In order to have the effect of increasing the resistivity of the silicon wafer in the manner discussed above, the deep level impurity must introduce one or more “deep energy levels” within the band gap of the silicon. These “deep energy levels” must be separated in energy by at least 0.3 eV from the relevant band. For donor states or levels, the relevant band is the conduction band whereas for acceptor states or levels, the relevant band is the valence band. Thus, a donor level is a deep energy level if it is separated from the conduction band by at least 0.3 eV (regardless of how close it may be to the valence band). Similarly, an acceptor level is a deep energy level if it is separated from the valence band by at least 0.3 eV (regardless of how close it is to the conduction band).

Some advantages of embodiments of the present process in the presence of thermal donor generation are given below.

A further system constraint is the possible occurrence of so-called “Thermal Donors”. These are common oxygen related defects that can arise during the final stages of device processing during heat treatments in the range of about 400-550° C. and are commonly formed in variable concentrations in most device processes. They result in the generation of additional electrons which, if in sufficiently high concentrations, can affect the final resistivity of the silicon wafer. It is a very significant problem for attempts at producing highly resistive material by means of simply reducing dopant concentration when using oxygen containing Czochralski-grown silicon, the main industrial form of silicon. In many cases the addition of even the tiniest concentration of these Thermal Donors can have disastrous effects. For example, in order to achieve about 5 kOhm-cm by means of simply reducing the phosphorus concentration of the silicon wafer, [P] must be limited to a maximum of about 1×10¹² cm⁻³. Under these conditions, an added Thermal Donor concentration of on the order of just 1×10¹² cm⁻³ would be sufficient to strongly decrease the final wafer resistivity. The generation of such small quantities of thermal donors in conventional Czochralski-grown silicon is nearly impossible to avoid, adding yet another huge challenge to the already daunting practical task of achieving the required low levels of phosphorus concentration. Various complex schemes of reducing the oxygen concentration of Czochralski-grown silicon wafers have been proposed in order to limit the negative effects of thermal donors on high resistivity material.

Embodiments of the present invention however offer a significant practical improvement. While Thermal Donors can affect the final resistivity in deep level impurity impregnated silicon wafers (e.g. gold doped silicon), generally far greater concentrations of Thermal Donors are required before measurable resistivity degradation occurs. The task of limiting the concentration of thermal donors becomes far easier with the resistivity controlled by gold diffusion and generally does not require overly strict practical limitations.

It has been found that high temperature treatments used in device fabrication steps after the impregnation of the silicon wafer can cause large reductions in the resistivity.

It is thought that this reduction may be due to clustering of the deep level impurities, described for the case of Au in Si in an academic study by Morooka in Japanese Journal of Applied Physics 25, no. 8 1986, p 1161. Such clustering would be effective to remove some of the Au from its substitutional sites and thus render it electrically inactive, which would result in loss of resistivity. Morooka associates with the clustering process a characteristic time T which depends on the Au concentration and the anneal temperature. T is seen to decrease with increasing temperature and with increasing Au concentration in the ranges investigated. For temperatures such that the solid solubility of the Au is close to the actual Au concentration or higher, clustering will not take place since there will be no thermodynamic driving force or it will be too small to be effective.

Extrapolation of Morooka's data to higher temperatures, even when not taking into account the fact that clustering will be reduced/stop as the Au concentration approaches/moves below the solid solubility as the temperature is increased, suggests that at concentrations of Au of 5×10¹⁵ clustering would take of order 5000 s even at a temperature of 875 degrees C. In practice the time is expected to be longer because at this temperature the driving force would be significantly reduced. However, for concentrations higher than this and/or different annealing temperatures, it is expected that the clustering time would be so short that the increase in resistivity due to substitutional Au would be lost during reasonably short processing times. For example, the inventors' experiments have demonstrated that a Au concentration of 1×10¹⁷ at 700 C would cluster in just a few minutes. Moreover, although an additional high temperature anneal, designed to dissolve the clusters and return the Au to the substitutional sites, works in principle, the temperatures required are incompatible with modern semiconductor devices and could not be used.

Taking together knowledge of the concentration of Au required to produce high resistivity material and the Au concentration dependence of the clustering time we can see that there are some combinations of silicon wafer dopant concentration and Au concentration which deliver highly resistive material whilst rendering the clustering sufficiently slow to be of little practical importance.

The fact that Au produces highly resistive Si has been known for decades but even though there has been a need for highly resistive material it has never been used. One reason for this is the risk of contamination of other devices. However, there are other obstacles to overcome, in terms of identifying suitable Au concentrations and starting wafer types, which may also have contributed to the lack of development in this area.

As described above, producing highly resistive material by Au works by the deep levels of the Au compensating the shallow levels of the residual dopant atoms. Those hardest to remove from Cz Si are B. A logical approach for making highly resistive material using Au would be to start with wafers with the lowest possible B concentration so that the dopants are most easily compensated. However, it has been found that, surprisingly, higher resistivities are obtained for n-type materials than for p-type materials. This is illustrated by FIG. 7, which shows calculated values for the resistivity of gold doped silicon at 298 K for material containing either 1×10¹⁴ cm⁻³ boron (nominally p-type; lower curve) or 1×10¹⁴ cm⁻³ phosphorous (nominally n-type; upper curve). It shows that for p-type material the resistivity increases monotonically with increasing gold concentration whilst for the n-type substrate resistivity tends to vary more quickly and peaks at an intermediate gold concentration (in this case around 1×10¹⁵ cm⁻³) before decreasing at higher gold concentrations. The peak resistivity obtained for an n-type substrate is higher than that which can be achieved for a p-type substrate. The inventors thus realised that an improvement can be obtained by intentionally increasing the shallow dopant concentration by doping the material n-type.

It might also be considered natural to introduce large amounts of Au since this makes compensation complete and also makes the material more resistant against the production of thermal donors. Thermal donors are produced from clustering oxygen atoms and they donate electrons into the conduction band, compensating any holes and even turning the material n-type and increasing the free electron concentration. This is generally bad from the point of view of wanting high resistivity material but the Au will compensate for both p and n-type material so will cope with this so long as there is enough Au present. In addition, if there are electric fields present in the material, due to voltages in the devices fabricated on it, especially immediately under the dielectric, they can induce free carriers in the same way as a voltage applied to the gate of a Field Effect Transistor (FET) induces free carriers in the channel under the gate oxide. If this were to happen in our high resistivity material (and it sometimes does when FZ is used for this purpose) it would ruin the high resistivity effect. However, in Au doped material the Fermi level is pinned so that even when a field is present it does not move and the material remains highly insulating. Thus, again, to make this effect as strong as possible one would expect that it would be a good idea to add lots of Au. However, the inventors have realised that this is not necessarily true because too much Au leads to clustering.

An alternative line of thinking might suggest that, to minimise processing time and expense, as little Au as possible should be used to compensate the shallow dopants. But the inventors have realised that this too would be wrong because this would not give sufficient protection from the thermal donors and field induced carriers described above.

The inventors have realised that a fairly narrow range of doping concentrations yield optimum characteristics (e.g. protection against thermal donors and field induced carriers without inducing clustering). The inventors have further found that this realisation can be exploited most efficiently by ensuring that the deep level impurities are distributed uniformly.

At present the practical lower limit to the residual boron concentration in commercial silicon wafers is of the order of 5×10¹³ cm⁻³ and the maximum allowable Au concentration before clustering becomes significant is expected to be of the order of about 5×10¹⁴ cm⁻³ to about 1×10¹⁶ cm⁻³, from 1×10¹⁵ cm⁻³ to about 5×10¹⁶ cm⁻³, or from about 7×10¹⁵ cm⁻³ to about 2×10¹⁶ cm⁻³. Arranging for the maximum Au concentration to be within these ranges would provide sufficiently high resistivity in n-type material with a doping concentration up to about 5×10¹³ cm⁻³ to 1×10¹⁵ cm⁻³ (for maximum Au concentrations in the range of about 5×10¹⁴ cm⁻³ to about 1×10¹⁶ cm⁻³), up to about 1×10¹⁴ cm⁻³ to 5×10¹⁵ cm⁻³ (for maximum Au concentrations in the range of about 1×10¹⁵ cm⁻³ to about 5×10¹⁶ cm⁻³) or up to about 7×10¹⁴ cm⁻³ to 2×10¹⁵ cm⁻³ (for maximum Au concentrations in the range of about 7×10¹⁵ cm⁻³ to about 2×10¹⁶ cm⁻³), or in p-type material with a doping less than about 2×10¹⁴ cm⁻³. Thus the preferred range of shallow doping concentrations is of the order up to about 5×10¹³ cm⁻³ to 1×10¹⁵ cm⁻³ n-type, up to about 1×10¹⁴ cm⁻³ to 5×10¹⁵ cm⁻³ n-type, or up to about 7×10¹⁴ cm⁻³ to 2×10¹⁵ cm⁻³ n-type, and less than 2×10¹⁴ cm⁻³ p-type.

Sub-optimal variations are possible, of course. For example, if lower shallow doping concentrations are used with levels of Au concentration that are more appropriate to higher shallow doping concentrations, we would effectively be operating in a regime that is to the right of the peak in the curve of resistivity against Au concentration (such as that shown in FIG. 7, but adapted to reflect the lower shallow doping concentration). If the Au concentration is lowered to correspond to the lower shallow doping concentration it may be possible to work again at the peak in the curve of resistivity against Au concentration, but the material would now be more susceptible to thermal donors and stray fields due to the lower concentration of Au. In general, the preference is to use as much Au as possible while avoiding clustering problems (i.e. of the order of about 1×10¹⁵ cm⁻³ to about 5×10¹⁶ cm⁻³, more particularly about 7×10¹⁵ cm⁻³ to about 2×10¹⁶ cm⁻³) and then match the starting n-type shallow dopant concentration to this to give a peak resistivity.

As discussed previously, the in-diffusion of gold results in a symmetrical concentration profile in depth: a “U-shaped” profile. It was previously thought that this U-shaped profile might be helpful because it means higher concentrations of gold (and, it was thought, higher resistivity) near the surface of the silicon wafer adjacent to the active devices, where high resistivity is particularly beneficial. However, the above insight suggests that divergent concentrations of the gold might instead cause clustering and loss of resistivity in these regions.

For example, in the absence of counter-measures, if impregnation is carried out in a standard manner with the aim of achieving a gold concentration of about 5e15 in the bulk of the silicon wafer (for example one hour at 1050 C), it is expected that the higher concentrations nearer the surfaces, associated with the U-shaped profile, would be sufficient to cause clustering. If the annealing is adapted to reduce the total amount of Au until clustering no longer occurs near the surface, the concentration will tend to be too low in the bulk properly to compensate the free carriers, leading to unacceptably low resistivity in the bulk.

Based on the above, the inventors have recognized that the Au (or other deep level impurity) concentration needs to be entirely within a narrow window (high enough to compensate the free carriers but low enough to prevent clustering) to achieve the required high resistivity. This is difficult or impossible to achieve for all or even most positions with the silicon wafer, including in particular the region adjacent to the devices (near a surface of the silicon wafer, for example within about 30 to 50 microns of the surface), where a typical U-shaped concentration profile is present, because of the relatively large variation of concentration with position.

According to disclosed embodiments, these issues are addressed by modifying the impregnation step to avoid or attenuate the “U-shaped” concentration profile.

According to an example embodiment, the impregnation step is performed in such a way that the ratio between the maximum concentration of deep level impurities in the silicon wafer and the average concentration of the deep level impurities in the silicon wafer (i.e. the average taken over the whole of the silicon wafer) is less than 7:1 (i.e. 7). Preferably, the ratio is less than 3, more preferably less than 1.5.

FIG. 2 illustrates attenuation of the “U-shaped” concentration profile. Here, the left part of the diagram is a graph of concentration (horizontal axis) of deep level impurities in a treated silicon wafer 4 against depth from a first surface 10 of the silicon wafer 4. The curve 14 shows a U-shaped profile that is attenuated relative to the profile that would result from impregnating a silicon wafer in the standard way (without any special steps being taken to avoid or attenuate the U-shaped profile—for example using a standard in-diffusion treatment where the rate limiting step is the rate of out-diffusion of Si self interstitials). The U-shaped profile is attenuated in the sense that the maximum concentration Cmax is relatively close to the minimum (bulk) concentration Cmin. This will tend to be the case where the ratio between the maximum concentration of deep level impurities in the silicon wafer Cmax and the average concentration of the deep level impurities in the silicon wafer is relatively small. As an alternative parameterization of the degree to which the U-shaped profile is avoided or attenuated, it is possible to make a comparison between the average concentration within a given depth of a surface of the silicon wafer and the overall average concentration in the silicon wafer.

For example, it is preferable that the impregnating step is carried out in such a way that the ratio of the average concentration of the impurities within a depth d of a first planar surface of the silicon wafer to the average concentration of the impurities in the silicon wafer is less than a threshold value X. In FIG. 2, this would correspond with the ratio of the average concentration within the hatched zone above the broken line at depth=d1 in the silicon wafer 4 to the average concentration for the whole silicon wafer 4 being less than the threshold value X. Alternatively or additionally, a similar constraint can be applied at the bottom surface 12, for example requiring that the ratio of the average concentration within the cross-hatched zone below the broken line at depth=d2 in the silicon wafer 4 to the average concentration in the whole silicon wafer 4 be less than the same threshold X or a different threshold.

Preferably, the depth d (e.g. d1, d2) is 15 microns, more preferably 5 microns, more preferably 1 micron. The smaller values are more preferable because the concentration profile can be quite strongly spiked at the surface.

Preferably, X is 7, more preferably 3, more preferably 1.5.

FIGS. 3 to 6 illustrate schematically how the avoidance or attenuation of the U-shaped profile may be achieved in practice.

FIGS. 3 and 4 illustrate methods in which a controlled amount of impurity is incorporated in a first step (or series of steps), and the distribution of impurities is subsequently homogenized (made more uniform) in a second step (or series of steps). The amount of impurity is controlled so as to achieve a desired concentration or concentration range after the homogenization step. For example, the amount of impurity may be controlled so as to be within a threshold range R of a predetermined target value W_(T), where W_(T)=5×10¹⁵ cm⁻³×volume of silicon wafer (in cm³), and R is 2×10¹⁵ cm⁻³×volume of silicon wafer (in cm³), for example, in the case of Au as the deep level impurity. In other words the amount of impurity is controlled to give an average silicon wafer concentration of (5±2)×10¹⁵ cm⁻³ Au.

In the method of FIG. 3, implantation (step S302, which may consist of ion implantation, for example) is used to introduce the controlled amount of impurity, before the in-diffusion/homogenization anneal (step S304).

In the method of FIG. 4, the impurities are introduced by diffusion (also referred to as “in-diffusion”). This can be achieved by bringing a source into contact with the silicon wafer (step S402), for example by depositing a pure, or at least relatively concentrated, quantity of the impurity on a surface of the silicon wafer, and annealing the silicon wafer and source according to a predetermined temperature profile (step S404). The predetermined temperature profile, which represents the variation of the temperature with time during the annealing process (for example: a constant, predetermined, elevated temperature for a predetermined time), is chosen as a function of the nature of the source, and the type of impurity that is to be introduced, so that a predetermined amount of impurity is introduced (within normal error tolerances). The source is then removed to stop the in-diffusion (step S406) and an anneal (step S408) is carried out to spread the impurities uniformly through the bulk of the silicon wafer.

The temperature profile of the anneal (e.g. steps S304 and S408) may include a phase at a temperature above 1000 degrees C., for example, to ensure that process is completed relatively quickly. The optimal parameters to use for this process will depend on the type of deep level impurity. For example, Au is a relatively fast diffuser, so the anneal may be adequately performed at lower temperatures and/or over shorter times than for deep level impurities which diffuse more slowly.

FIGS. 5 and 6 illustrate an alternative approach in which the final anneal (of the type of step S304 or S408 for example) is not required (although it may still be used in addition, if desired, to further improve the uniformity of the impurity distribution). FIG. 5 is a flow diagram illustrating the method. FIG. 6 is a schematic side view of a silicon wafer 4 having a diffusion-inhibiting layer 18 and a source layer 16.

According to this method, a diffusion-inhibiting layer 18 is formed on a surface of a silicon wafer 4 (step S502). A source 16 of the impurity to be introduced is then applied to the outside surface of the diffusion-inhibiting layer 18 (step S504) such that the diffusion-inhibiting layer 18 lies between the silicon wafer 4 and the source 16, separating the source 16 from the silicon wafer 4 so that impurities can only enter the silicon wafer 4 via the diffusion-inhibiting layer 18.

As described above, in the absence of a diffusion-inhibiting layer 18, the rate at which deep level impurities move from a source on the silicon wafer surface to substitutional sites within the silicon wafer is limited, for various types of deep level impurity (e.g. Au) and impregnation annealing temperatures (e.g. above 800 degrees C.), by the rate at which Si self interstitials diffuse out to the surface of the silicon wafer. This is the effect which leads to the U-shaped profile.

The diffusion-inhibiting layer 18, and the temperature profile that is used during the impregnation annealing (step S506) are configured such that the rate at which impurities enter the bulk is reduced, preferably until this becomes the rate limiting step for introducing the impurities into the silicon wafer, instead of the rate at which the Si self interstitials move out of the material. The U-shaped profile is thus avoided or attenuated. The source 16 and, optionally, the diffusion-inhibiting layer 18 also, are removed after the impregnation annealing (step S508).

The temperature profile of the impregnation anneal 5506 with the diffusion-inhibiting layer 18 is preferably chosen to include a phase at a temperature above 1000 degrees C., preferably in excess of 1100 degrees C., to ensure the process is completed relatively quickly. As mentioned above, the optimal parameters to use will depend on the type of deep level impurity being used.

Alternatively or additionally, the in-diffusion may be performed at relatively low temperatures for long periods of time. For example, in the case of Au as the deep level impurity, at 900 degrees C. the Au solubility is just over 2e15 and thus this would be an appropriate temperature to do an in-diffusion without the Au concentration becoming too high.

The inventors have found that thermal anneals of silicon doped with Au can cause a thin Au rich layer to be produced at the surface of wafers. This layer is to some extent conductive and would reduce the effective resistivity of the wafer if it were to be used as a substrate in a device. Such a layer can be observed after the impregnation anneal S506, for example, depending on the cooling rate after this anneal. The inventors have found that this Au rich layer can be removed by chemical etching in, for example, aqua regia or an aqueous potassium iodide/iodine solution. In an example it was found that a piece of Au doped silicon that showed an effective resistivity of ˜50 kohm cm when measured using a four point contact method immediately after an impregnation anneal, showed a resistivity of ˜150 kohm cm when re-measured after using a Au removing etch. However, if the wafer has a surface layer of another material, for example silicon oxide or a III-V semiconductor, then the Au rich layer can form at the interface between the two materials and in this case cannot be removed by a chemical etch. The application of a short, high temperature anneal followed by a rapid cool, for example as routinely used in Rapid Thermal Anneals (RTAs), can remove the Au rich layer by redistributing the Au deeper into the silicon. This process may be carried out on silicon either with or without the presence of surface layers of another material. The duration of this anneal step will typically be one to five minutes at a temperature of approximately 1150 C. The cooling rate after such an anneal should be greater than about 40 C per minute down to a temperature of around 650 C. Below about this temperature the cooling rate can be slower.

It has been found that annealing Au containing Si at high temperatures can induce clustering of the Au which reduces the number of deep levels in the material associated with the impurity. This process can change the resistivity of the material in an undesired way. These clusters of Au can be broken up by a relatively short, high temperature anneal at a temperature such that the concentration of Au in the material (including that in both the substitutional and clustered state) is below the solid solubility for Au in silicon at that temperature. The duration of this anneal may be of order 35% or less of the time used for the drive-in anneal which has previously been used to distribute the Au through the silicon. An example of such an anneal to break up Au clusters would be 1000 C for 20 minutes.

The precipitation of oxygen present in a silicon wafer can lead to the injection of silicon self interstitials that displace Au atoms lying on substitutional sites so as to move them onto interstitial sites which may change the resistivity of the material in an undesired way. The rate of oxygen precipitation is strongly dependent on (amongst other things) the concentration of oxygen interstitials present in the wafer. This concentration can be reduced by purposely precipitating much of the oxygen before Au is introduced into the wafer but it can also be reduced by the selection of Czochralski wafers that have been grown using the so called magnetic Czochralski process. In this process a strong magnetic field is applied to the silicon melt during ingot growth. This has the effect of damping convective currents in the melt which in turn reduces the amount of oxygen interstitials incorporated into the growing ingot. Typical oxygen concentrations in standard Czochralski (CZ) silicon are above 7×10¹⁷ cm⁻³ whereas for magnetic Czochralski (MCZ) silicon they are normally below 5×10¹⁷ cm⁻³. MCZ silicon is sometimes used where it is wished to suppress thermal donor generation (thermal donors are electrically active oxygen complexes whose rate of generation increases with increasing interstitial oxygen concentration). However, this functionality will not normally be relevant in the present application because the Au deep levels will effectively compensate for the thermal donor energy levels. The production of MCZ wafers is also more expensive than standard CZ wafers and MCZ wafers are mechanically weaker (their yield strength may be as much as 15% lower). Nevertheless, the inventors have recognised that the benefits described above in terms of reducing the displacement of substitutional Au onto interstitial sites make it attractive to use MCZ wafers for high resistivity Au doped silicon substrates despite the extra cost involved and the mechanically weaker material produced.

In the above description detailed references are made to Si, and in particular Czochralski Si, as the material forming the wafers that are impregnated with deep level impurities. However, the embodiments are not limited to Si: other materials in which the resistivity can be increased by impregnation with deep level impurities could be used as the wafer in any of the embodiments described.

Any of the aspects of the invention can be combined together in any combination. 

1. A method of processing a silicon wafer for use in a substrate for an electronic circuit, comprising: impregnating the silicon wafer with impurities that form one or more deep energy levels within the band gap of silicon, wherein at least one of said deep energy levels is positioned at least 0.3 eV away from the conduction band if the level is a donor level or at least 0.3 eV away from the valence band if the level is an acceptor level, wherein: said impregnating step is performed in such a way that the ratio between the maximum concentration of said impurities in said silicon wafer and the average concentration of said impurities in said silicon wafer is less than 7:1.
 2. A method according to claim 1, wherein: said impurities comprise gold and the maximum concentration of gold in said silicon wafer is in the range from about 5×10¹⁴ cm⁻³ to about 1×10¹⁶ cm⁻³; and said silicon wafer has a shallow level doping concentration in the range of from about 5×10¹³ cm⁻³ to about 1×10¹⁵ cm⁻³ n-type.
 3. A method according to claim 1, further comprising, after the impregnating step: removing a layer at the surface of the silicon wafer by etching; or performing an anneal to redistribute said impurities away from a surface layer.
 4. A method according to claim 1, wherein the silicon wafer is formed from silicon grown using the magnetic Czochralski method.
 5. A method according to claim 1, wherein: said silicon wafer has first and second planar surfaces; and said impregnating step is carried out in such a way that the ratio of the average concentration of said impurities within a depth d of said first planar surface to the average concentration of said impurities in said silicon wafer is less than a threshold value X.
 6. A method according to claim 5, wherein: d is one of the following: 15 microns, 5 microns, 1 micron; and X is one of the following: 7, 3, 1.5.
 7. (canceled)
 8. A method according to claim 5, wherein said impregnating step is carried out in such a way that the ratio of the average concentration of said impurities within the depth d of said second planar surface to the average concentration of said impurities in said silicon wafer is less than the threshold value X.
 9. A method according to claim 1, wherein: said impregnating step comprises controlling the amount of said impurity that is introduced into said silicon wafer so that it is within a threshold range R of a predetermined target value W_(T).
 10. A method according to claim 9, wherein said impregnating step comprises implanting said impurities into said silicon wafer.
 11. A method according to claim 9, wherein said impregnating step comprises an in-diffusion process consisting of: bringing a source of said impurity into contact with said silicon wafer; heating said silicon wafer according to a predetermined temperature profile; and removing said source of said impurity, wherein said source and temperature profile are configured such that the amount of said impurity that is introduced into said silicon wafer is within said threshold range R of said predetermined target value W_(T).
 12. A method according to claim 9, wherein said impregnating step further comprises annealing said silicon wafer to distribute said impurities more uniformly, said.
 13. (canceled)
 14. A method according to claim 9, wherein: said impregnating step comprises: applying a diffusion-inhibiting surface layer to a surface of said silicon wafer; bringing a source of said impurity into contact with said diffusion-inhibiting surface layer, such that impurities can enter said silicon wafer only via said diffusion-inhibiting surface layer; heating said silicon wafer according to a predetermined temperature profile; and removing said source of said impurity, wherein: said source and temperature profile are configured such that the amount of said impurity that is introduced into said silicon wafer is within said threshold range R of said predetermined target value W_(T); and said diffusion-inhibiting surface layer is configured such that the rate of diffusion of said impurities into said silicon wafer is reduced relative to the case where the source is in direct contact with said silicon wafer.
 15. A method according to claim 14, wherein said source, temperature profile and diffusion-inhibiting surface layer are configured such that the rate of diffusion of impurities through the diffusion-inhibiting surface layer is the rate limiting step in the impregnation process.
 16. A method according to claim 1, wherein: said impurities comprise gold and the maximum concentration of gold in said silicon wafer is in the range from about 5×10¹⁴ cm⁻³ to about 1×10¹⁶ cm⁻³.
 17. A method according to claim 1, wherein: said silicon wafer has a shallow level doping concentration in the range of from about 5×10¹³ cm⁻³ to about 1×10¹⁵ cm⁻³ n-type.
 18. A method according to any one of claims 1 to 15, wherein: said silicon wafer has a shallow level doping concentration less than about 2e14 cm⁻³ p-type.
 19. A method of processing a silicon wafer for use in a substrate for an electronic circuit, comprising: impregnating the silicon wafer with impurities that form one or more deep energy levels within the band gap of silicon, wherein at least one of said deep energy levels is positioned at least 0.3 eV away from the conduction band if the level is a donor level or at least 0.3 eV away from the valence band if the level is an acceptor level; and after the impregnating step: removing a layer at the surface of the silicon wafer by etching; or performing an anneal to redistribute said impurities away from a surface layer.
 20. (canceled)
 21. A substrate for an electronic circuit, comprising: a silicon wafer impregnated with impurities that form one or more deep energy levels within the band gap of silicon, wherein at least one of said deep energy levels is positioned at least 0.3 eV away from the conduction band if the level is a donor level or at least 0.3 eV away from the valence band if the level is an acceptor level, wherein: the ratio between the maximum concentration of said impurities in said silicon wafer and the average concentration of said impurities in said silicon wafer is less than 7:1.
 22. (canceled)
 23. A substrate according to claim 20, further comprising: a diffusion barrier layer, formed on a surface of the silicon wafer and providing an outer surface on which a device layer may be formed, said diffusion barrier layer having the property of substantially preventing diffusion of said impurities through it.
 24. A substrate according to claim 20, further comprising a device layer having electronically functional components.
 25. (canceled)
 26. A device manufacturing method, comprising the following steps: impregnating a silicon wafer with impurities that form one or more deep energy levels within the band gap of silicon, wherein at least one of said deep energy levels is positioned at least 0.3 eV away from the conduction band if the level is a donor level or at least 0.3 eV away from the valence band if the level is an acceptor level; forming a device layer comprising electronically functional components; and after the impregnating step: removing a layer at the surface of the silicon wafer by etching; or performing an anneal to redistribute said impurities away from a surface layer.
 27. A substrate according to any one of claim 20, wherein said impurities include one or more of the following: gold, silver, chromium, cobalt, palladium, platinum, vanadium and manganese; and the concentration of said impurities is in the range of 1013 to 1018 cm-3. 28-31. (canceled) 